The present invention concerns using a channel router to route connection networks in very large scale integrated (VLSI) circuits constructed using three layer metal gate array technology.
After logic circuitry for a VLSI circuit has been designed, placement algorithms are used to place the VLSI circuit logic efficiently upon a chip. For example, in gate array logic, logic cells are placed in logic circuitry rows. Intercell connectors for the logic cells are connected together with wire network. The wire networks are formed of layers of metal placed on the chip.
For example, in two layer metal gate array circuitry, logic cells are generally placed in logic circuitry rows separated by routing channels. Intercell connectors for the cells are placed at the boundary of a routing channel. A channel router is then used to connect networks of intercell connectors. The channel router routes wires within the routing channels so that a first layer of metal is used for wires running parallel to the routing channel (horizontal wires) and a second layer of metal is used for wires running perpendicular to the routing channel (vertical wires). Herein, wires running parallel to a routing channel or row are considered to be horizontal. Wires running perpendicular to a routing channel or row are considered to be vertical.
Channel routers require that intercell connectors be located at the boundaries of the routing channels. This serves to limit the complexity of design of channel routers as well as providing for quality routes.
In three layer metal gate array circuitry, space on the integrated circuit is used more efficiently by eliminating routing channels between logic circuitry rows. Instead, intercell routing is performed using the top two layers of metal (The bottom layer of metal is used in the implementation of the logic cells). Intercell connectors, i.e., pins, from the logic cells extend into the first metal layer. An area router is used to route the wires between the intercell connectors. Similar to channel routers, an area router routes wires so that a first layer of metal is used for wires running parallel to the logic circuitry rows (horizontal wires) and a second layer of metal is used for wires running perpendicular to the routing channel (vertical wires).
Area routers are generally more complex to implement than channel routers. This is because area routers need to be able to route pins which are randomly distributed. The increased complexity of area routers additionally results in the generation of routes which are placed inferiorly as compared to placements of routes by channel routers.